Integrated circuits utilize interconnects to transmit signals from one portion of the circuit to another portion of the circuit. Interconnects within an integrated circuit typically comprise wires (i.e., traces) formed in a metal layer of the integrated circuit. Each wire is associated with a resistance and a capacitance that is related to the physical design of the wire (e.g., cross section, length, etc.). Transmitting signals on these wires is not instantaneous. Changing a signal on the wire requires the wire to be charged or discharged. There is a time delay for a signal to travel down a wire that is characterized by an RC time constant associated with the wire (i.e., a resistance of the wire in ohms multiplied by a capacitance of the wire). Because both resistance of a wire and capacitance of a wire increase linearly with a wire's length, the time delay increases as a square of the wires length.
In order to decrease the time delay associated with a long interconnect, active circuit(s) can be introduced along the long interconnect to break the long interconnect up into multiple shorter interconnects. Because the time delay of the short interconnects, added together, is less than the time delay of the long interconnect, a relatively faster link can be provided over the same linear distance of the integrated circuit. FIG. 1A illustrates a conventional CMOS (Complementary Metal Oxide Semiconductor) repeater link 100, in accordance with the prior art. The link 100 includes a plurality of interconnects (e.g., 112, 114, 116, 118, etc.) connected to a number of repeaters (e.g., inverters 102, 104, 106, etc.). The repeaters shown in FIG. 1A are conventional CMOS inverters. It will be appreciated that an even number of repeaters (and an odd number of interconnects) may be used to ensure the signal at the end of the link 100 is the same polarity as the signal at the beginning of the link 100. The repeaters reduce the delay of the link 100 even though an “insertion delay” (i.e., delay incurred to transmit a signal from the input of a repeater to the output of the repeater) is introduced for each repeater that is inserted into the link 100.
The link 100 may be used to transmit a signal, A, from one end of the link 100 to the other end of the link 100. For example, the interconnect 112 may be charged to high potential (Vdd) to match a logic high state of signal A. The inverter 102 then discharges interconnect 114 to a low potential (Vss) to match an inverted state of signal A, i.e., a logic low state of signal Ā. The inverter 104 then charges interconnect 116 to a high potential (Vdd) to match an inverted state of signal Ā, i.e., a logic high state of signal A. The inverter 106 then discharges interconnect 118 to a low potential (Vss) to match an inverted state of signal A, i.e., a logic low state of signal Ā, and so forth until the end of the link is reached and the last interconnect is charged to a high potential (Vdd) to match a logic high state of signal A at the beginning of the link 100.
FIG. 1B illustrates a conventional CMOS inverter 120, in accordance with the prior art. One or more of the inverters 102, 104, and 106, may be implemented as the inverter 120. When an inverter 120 is inserted into a link 100, a first current flows from the link 100 to an input of the inverter 120 to the gates of transistors 121 and 122. Either transistor 121 or 122 is enabled. When transistor 121 is enabled and transistor 122 is disabled, a second current is generated from Vdd to the output of the inverter 120 through the transistor 121. When transistor 121 is disabled and transistor 122 is enabled, the second current is generated from the output to ground through the transistor 122. The input is coupled to a first node of the link 100 and the output is coupled to a second node of the link 100, so that the link 100 is not a continuous wire. For example, the input of an inverter 120 implementing the repeater 102 is coupled to a first node at an end of the interconnect 112 and the output of the inverter 120 implementing the repeater 102 is coupled to a second node at an end of the interconnect 114. The inverter 120 replaces a signal received at the input with a second signal (i.e., an inverted version of the first signal) that is generated at the output of the inverter 120. The inverter 120 interrupts the first current and generates the second current to transmit the signal from the input to the output. Importantly, the inverter 120 only transmits a signal in one direction, from the input to the output.
While the repeaters reduce the delay of the link 100, the repeaters also limit the direction of the link 100. In other words, signals may only be transmitted in one direction, from the input of inverter 102 to the output of inverter 106. Without the repeaters, signals may be transmitted by the link 100 in both directions. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.